Complementary metal-oxide-semiconductor (CMOS) technology is a dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET) has provided significant improvement in the speed, performance, circuit density, and cost per unit function of semiconductor chips over the past few decades. Significant challenges are faced when CMOS devices are scaled into the sub-100 nm regime. An attractive approach for additional improvement of CMOS transistor performance exploits strain-induced band-structure modification and mobility enhancement to increase transistor drive current. Enhanced electron and hole mobilities may improve the drive currents of N-channel and P-channel MOSFETs, respectively. Enhanced electron and hole mobilities may be achieved by having silicon (Si) or a silicon alloy such as silicon germanium (SiGe) or silicon carbon (SiC) in the channel region under strain. For silicon transistors with source-to-drain direction oriented along a [110] crystal direction, silicon channel under tensile strain enhances electron mobility and Si under compressive strain enhances hole mobility.
Strained channel transistors known in the art have materials known as stressors. The term stressor may define a semiconductor material that imposes stress on another semiconductor material. FIGS. 1a-1c show regions in which stressors are commonly formed. An underlying substrate region 102 shown in FIG. 1a may comprise a stressor. As shown in FIG. 1b, source and drain regions 108 may comprise a material that stresses the channel from adjacent sides. Materials in the channel etch stop layer 114 may impose a stress on the channel region 110 from above, as shown in FIG. 1c. 
Bi-directional arrows in the channel region 110 of FIGS. 1a-1c show that the strain imposed on the channel region 110 may be tensile or compressive. Compressing a material in a channel region of a transistor typically enhances hole flow and may improve P-channel transistor performance. Tensile stress in a channel region of a transistor typically enhances electron flow and may improve N-channel transistor performance.
FIG. 2 shows a strained channel transistor 120 formed in a material layer structure 122. The material layer structure includes a buried oxide (BOX) layer 123. A Si layer 128 covers the BOX layer 123. A graded SiGe layer 124 overlies the Si layer 128. A relaxed SiGe layer 130 covers the graded SiGe layer 124 and acts as a stressor to the overlying strained Si layer 126. Source and drain regions 132 and a channel region 134 are in the strained Si layer 126. As shown in FIGS. 3a and 3b, the thick relaxed SiGe layer 130 imposes a biaxial tensile strain on the thin Si layer 126. The relaxed SiGe layer 130 stretches the strained Si layer 126 along a width and a length of the channel region 134.
Referring to FIG. 2, the strained channel transistor 120 formed within the material layer structure 122 includes the graded SiGe layer 124. The graded SiGe layer 124 may increase manufacturing cost, in part due to the time required to grow multiple layers of Si with increasing concentrations of germanium (Ge). Another limitation of having a SiGe layer in the strained channel transistor 120 may be lattice dislocations in the stressed layer. As shown in FIG. 2, dislocations 136 in the SiGe layer may propagate to the strained Si layer 126, possibly causing faulty or poor transistor 120 performance, such as increased junction leakage.
Subsequent fabrication steps, including thermal processing steps involved in forming the transistor 120 in a strained Si layer 126, may cause the amount of strain in the strained Si layer 126 to diminish, reducing strain in the channel region 134. Reduced strain in the channel region 134 may result in decreased transistor 120 performance.
In U.S. Pat. No. 6,621,131 B2, entitled “Semiconductor Transistor Having a Stressed Channel,” Muthy et al. disclose a strained channel transistor 140 shown in FIG. 4a. SiGe formed in the source and drain regions 142 impose a stress on Si material in the channel 144 from adjacent sides. Murthy et. al. recognize, however, that the device of FIG. 4a results in non-uniform strain as shown in FIG. 4b. Lines 146 in FIG. 4b indicate direction of stress in the channel 144 between the source and drain regions 142. A more dense spacing between the lines 146 indicates a larger stress and a larger spacing between the lines 146 indicates a smaller stress. FIG. 4b shows a decrease in strain related to the depth D and the width Wc of the channel 144.
Various shortcomings in the prior art can be overcome and advantageous features can be obtained by the provision of a strained channel transistor having a stressed channel with stressing material below as well as on adjacent sides of the channel region.